library verilog;
use verilog.vl_types.all;
entity branch is
    port(
        branch          : in     vl_logic_vector(2 downto 0);
        rs              : in     vl_logic_vector(15 downto 0);
        j               : in     vl_logic;
        jump            : out    vl_logic
    );
end branch;
